1. Field of the Invention
The present invention generally relates to a redundant circuit, and more particularly, to a redundant circuit for a Dynamic Random Access Memory (DRAM).
This application relies for priority on Japanese patent application, Serial Number 215170/1998, filed Jul. 30, 1998, which is incorporated herein by reference in its entirety.
2. Description of the Related Art
As memory capacity and memory density of semiconductor memory devices have increased in recent years, such devices have been provided with both redundant memory cells and normal memory cells. If one of the normal memory cells has a defect, the redundant memory cell is substituted for the defective normal memory cell. As a result, a faulty chip may be repaired or fixed. In this technical field, the technique mentioned above is widely used.
In a conventional semiconductor memory device, which has a redundant memory cell, there is a possibility that a column line associated with the defective memory cell and a redundant column line associated with the redundant memory cell are activated at the same time. Therefore, it is necessaty to delay the time when the redundant column line is activated so that the defective memory cell and data of the redundant memory cell are not read out to a data bus at the same time. As a result, an access time of the semiconductor memory device is increased.
Consequently, there has been a need for an improved semiconductor memory device.
It is an object of the present invention to provide a semiconductor memory device that may reduce an access time when a redundant column line is activated.
It is another object of the present invention to provide a semiconductor memory device that has a reduced chip area.
It is another object of the present invention to provide a semiconductor memory device that may reduce the number of defect column address signal lines.
According to one aspect of the present invention, for achieving one or more of the above objects, a semiconductor memory device is provided that includes word lines, normal bit lines, and a redundant bit line. The semiconductor memory device also includes normal memory cells, each of which is coupled to one of the word lines and one of the normal bit lines, and each of which stores data. The semiconductor memory device also includes redundant memory cells, each of which is coupled to one of the word lines and the redundant bit line. The semiconductor memory device further includes a first address signal output circuit outputting a first address signal that indicates an address of one of the normal bit lines, a second address signal output circuit outputting a second address signal indicating an address of one of the normal bit lines in which a defective memory cell is coupled, and a coincidence circuit that receives the first address signal, and the second address signal and which selects the redundant bit line when the first address signal coincides with the second address signal. The semiconductor memory device further includes a logic circuit, which receives the first address signal and the second address signal, which selects one of the normal bit lines according to the first address signal, and which is inhibited from selecting the normal bit line corresponding to the second address signal.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims, and the accompanying drawings.